The PGA309 has a user-accessible test pin （Test， pin 9） that stops the internal state machine cycle and

　　enables the output drive （VOUT） when it is brought high （logic ‘1’）。 This mode can be used for simple

　　troubleshooting or initial configuration diagnostics during the system design phase. During normal

　　（stand-alone） operation， the Test pin must be pulled or shorted to GND （logic ‘0’）。 If the Test pin is pulled

　　high at any time， the following conditions occur：

　　? The PGA309 internal state machine is interrupted and reset to its initial state. Any EEPROM

　　transactions are interrupted and the two-wire bus is released.

　　? The PGA309 output （VOUT） is enabled.

　　? All internal registers remain at their current values. If the Test pin is high when the supply becomes

　　valid， the registers stay in the initial （POR） state，and output is enabled immediately.

　　? An external controller can modify any of the writeable PGA309 registers using either a one-wire or

　　two-wire digital interface.

　　? The Test pin has a 25μA typical pull-down current source.