The ATM Forum Technical Committee March 21, 1994:

1. Introduction....1
1.1 Document Purpose.1
1.2 Document Scope....1
1.3 Current Level1
2. Motivation and Goals2
3. Functional Description...3
3.1 Conventions3
3.2 Interface Rates..3
3.3 Device Capabilities3
3.3.1 Synchronization.3
3.3.2 Rate Matching...3
3.3.3 Cell Processing..4
3.4 Relationship of Signals4
4. Transmit Interface.5
4.1 Signals..5
4.2 Operation and Timing..5
4.2.1 Octet-Level Handshake6
4.2.2 Cell-Level Handshake..6
4.2.3 Examples6
4.2.4 Timing Specifications.8
5. Receive Interface...9
5.1 Signals..9
5.2 Operation and Timing..10
5.2.1 Octet-Level Handshake10
5.2.2 Cell-Level Handshake..10
5.2.3 Examples10
5.2.4 Timing Specifications.11
6. 16-Bit Mode...13
6.1 Purpose..13
6.2 Cell Format.13
6.3 Signals..13
7. Summary..15
7.1 Transmit Interface Signals....15
7.2 Receive Interface Signals15

The ATM Forum Technical Committee June 1995 :

1. INTRODUCTION 1
1.1. Document Purpose and Background 1
1.2. Scope 1
1.3. Statement of Compatibility with Level 1 Document 2
1.4. Document Contents 2
2. FUNCTIONAL DESCRIPTION 3
2.1 Conventions 3
2.2. Terminology related to Utopia Scope 3
2.3. Other Terminology 5
2.3. Reference Model and Configurations 5
2.4. Interface Rates 7
2.5. Device Capabilities 7
2.6. Cell Processing 7
3. AMENDED LEVEL 1 SPECIFICATION 8
3.1. Introduction and Motivation 8
3.2. Level 1 Section 4.2 on Transmit Operation 8
3.3. Level 1 Section 5.2 on Receive Operation 12
4. MPHY DATA PATH OPERATION 16
4.1. Signals 16
4.2. Operation with 1 TxClav & 1 RxClav Signal 18
4.3 Direct status indication 25
4.4 Multiplexed status polling 30
5. TIMING DETAILS AT 25, 33 AND 50 MHZ 35
5.1 A.C. characteristics 35
5.2 D.C. characteristics 45
5.3 Signals TxRef* and RxRef* 47
6. DATA PATH SIGNAL SUMMARY 48
6.1. Transmit Interface Signals 48
6.2. Receive Interface Signals 48
APPENDIX 1. METHOD TO SUPPORT A LARGER NUMBER OF PHYS 49
A1.1. Example 49
A1.2 Special cases 50
A2.3 Impact on the PHY Layer 50
A2.4 Impact on the ATM Layer 50
APPENDIX 2. MANAGEMENT INTERFACE 51
A2.1 Scope 51
A2.2 Introduction 51
A2.3 Serial interface 51
A2.4 Parallel interface 60
A2.5 D.C. characteristics 64
A2.6 Notes 65
APPENDIX 3. REFERENCES 66