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SM320DM642-HIREL 視頻/成像定點(diǎn)數(shù)字信號(hào)處理器

數(shù)據(jù):

描述

The C64x™ DSPs (including the SM320DM642-EP device) are the highest-performance fixed-point DSP generation in the C6000 DSP platform. The DM642 device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000 DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mbps Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels — A and B with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x™ DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins that can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all eight serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output.For more details on the VIC port, see the TMS320C64x™ DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception.For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000™ DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the DM642 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM642 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

特性

  • 受控基線
    • 一個(gè)裝配/測(cè)試/制造現(xiàn)場(chǎng)
  • 增強(qiáng)的減少制造資源(DMS)支持
  • 增強(qiáng)產(chǎn)品更改通知
  • 資格譜系(1)
  • 高性能數(shù)字媒體處理器
    • 2 ns,1.67 ns,1.39 ns指令周期時(shí)間
    • 720 MHz時(shí)鐘頻率(500/600 MHz設(shè)備僅供產(chǎn)品預(yù)覽)
    • 八32位指令/周期
    • 5760 MIPS
    • 完全軟件兼容C64x™
  • VelociTI.2™擴(kuò)展到VelociTI™
    高級(jí)超長(zhǎng)指令字(VLIW)TMS320C64x™DSP內(nèi)核
    • 具有VelociTI.2™擴(kuò)展的八個(gè)高度獨(dú)立的功能單元:
      • 六個(gè)ALU(32/40位),每個(gè)時(shí)鐘周期支持單32位,雙16位,或四位8位算術(shù)
      • 兩個(gè)乘法器支持每個(gè)時(shí)鐘周期的四個(gè)16×16位乘法(32位結(jié)果)或八個(gè)8×8位Mu每個(gè)時(shí)鐘周期的ltiplies(16位結(jié)果)
    • 具有不對(duì)齊支持的加載存儲(chǔ)架構(gòu)
    • 64位32位通用寄存器
    • 指令包裝減少代碼大小
    • 所有指令條件
  • 指令集功能
    • 字節(jié)可尋址(8/16 /32/64位數(shù)據(jù))
    • 8位溢出保護(hù)
    • 位域提取,設(shè)置,清除
    • 歸一化,飽和度,位計(jì)數(shù)
    • VelociTI.2™增加正交性
  • L1 /L2內(nèi)存架構(gòu)
    • 128K位(16K字節(jié))L1P程序緩存(直接映射)< /li>
    • 128K位(16K字節(jié))L1D數(shù)據(jù)高速緩存(雙向設(shè)置關(guān)聯(lián))
    • 2M位(256K字節(jié))L2統(tǒng)一映射RAM /高速緩存(靈活RAM /高速緩存
      分配)
  • Endianess:Little Endian,Big Endian
    • 64位外部存儲(chǔ)器接口(EMIF)
    • 無異常的異步接口< br>存儲(chǔ)器(SRAM和EPROM)和
      同步存儲(chǔ)器(SDRAM,SBSRAM,ZBT SRAM,和FIFO)
  • 1024M字節(jié)總可尋址外部存儲(chǔ)空間
  • 增強(qiáng)型直接存儲(chǔ)器訪問(EDMA)控制器(64個(gè)獨(dú)立通道) )
  • 10/100 Mbps以太網(wǎng)MAC(EMAC)
    • IEEE 802.3兼容
    • 媒體獨(dú)立接口(MII)
    • 八個(gè)獨(dú)立傳輸( TX)通道和
      一個(gè)接收(RX)通道
  • 管理數(shù)據(jù)輸入/輸出(MDIO)
  • 三個(gè)可配置視頻端口
    • 為通用視頻解碼器和編碼器設(shè)備提供無線I /F
    • 支持多個(gè)分辨率/視頻標(biāo)準(zhǔn)
  • VCXO插值控制端口(VIC )
    • 支持音頻/視頻同步
  • 主機(jī)端口接口(HPI)[32/16位]
  • 32位/66 MHz,3.3V外設(shè)組件
    互連(PCI)主/從接口
    符合PCI規(guī)范2.2
  • 多通道音頻串行端口(McASP)
    • 八個(gè)串行數(shù)據(jù)引腳
    • 各種各樣的I 2 S和類似的比特流格式
    • 集成數(shù)字音頻I /F發(fā)送器支持S /PDIF,
      IEC60958-1,AES-3,CP-430格式
  • 內(nèi)部集成電路(I 2 C Bus™)
  • 兩個(gè)多通道緩沖串行端口(McBSP)
  • 三個(gè)32位通用定時(shí)器< /li>
  • 16個(gè)通用I /O(GPIO)引腳
  • 靈活的PLL時(shí)鐘發(fā)??生器
  • IEEE-1149.1(JTAG)邊界掃描兼容
  • < li> 548針球柵陣列(BGA)封裝,0.8 mm球間距
  • 0.13μm/6級(jí)Cu金屬工藝(CMOS)
  • 3.3 VI /O,1.4 V內(nèi)部( A-500,A-600,-600,-720)

(1)符合JEDEC和行業(yè)標(biāo)準(zhǔn)的組件認(rèn)證,確??煽吭跀U(kuò)展的溫度范圍內(nèi)操作。這包括但不限于高加速應(yīng)力測(cè)試(HAST)或偏壓85/85,溫度循環(huán),高壓釜或無偏HAST,電遷移,鍵合金屬間壽命和模塑化合物壽命。此類鑒定測(cè)試不應(yīng)被視為超出規(guī)定的性能和環(huán)境限制使用該組件的合理性。
C64x,VelociTI.2,VelociTI,TMS320C64x,C6000,TMS320C6000,DM64x,C62x,TMS320C62x,TMS320C67x,Code Composer Studio,DSP /BIOS,XDS,TMS320是Texas Instruments的商標(biāo)。
所有其他商標(biāo)均為其各自所有者的財(cái)產(chǎn)。

參數(shù) 與其它產(chǎn)品相比 C6000 DSP

 
DSP
On-Chip L2 Cache/RAM
Operating Temperature Range (C)
Rating
SM320DM642-HIREL
1 C64x    
128 KB    
-40 to 105    
Catalog    

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